The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving reactive ion etching.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or xe2x80x9cflip-chipxe2x80x9d packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is xe2x80x9cflippedxe2x80x9d over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is bulk silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for analyzing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
For flip-chips and other dies requiring or benefiting from back side access, techniques have been developed to access the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of nIR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using nIR microscopy. For a die that is 725 microns thick, at least 625 microns of silicon is removed before nIR microscopy can be used.
Thinning the die for analysis of an IC requiring or benefiting from back side access is usually accomplished by first globally thinning, wherein the silicon is thinned across the entire die surface. The silicon is globally thinned to allow viewing of the active circuit from the back side of the die using nIR microscopy. Mechanical polishing and chemical-mechanical polishing are two example methods for global thinning. Using nIR microscopy, an area is identified for accessing a particular area of the circuit.
An example method for etching a semiconductor device is a form of dry etching called reactive ion etching (RIE). In a typical dry etch process, reactive species are first generated in a plasma. The species then diffuse to the substrate surface being etched, where they are adsorbed. A chemical reaction occurs, and a volatile by-product is formed. The by-product is then desorbed from the surface and diffused into the bulk of the gas. RIE is one such type of dry etching which is often used to selectively etch a substrate on which desired features of an integrated circuit have been defined using a process such as photo-lithography. In RIE, a process gas is introduced into a chamber. Plasma is generated in the chamber and used to create an etch gas from the process gas. The etch gas etches the substrate and creates volatile etch byproduct compounds which are evacuated from the chamber.
Near-infrared microscopy, however, generally requires that the surface through which an image is obtained is substantially flat and non-pitted. This requirement has made the use of RIE via the back side of semiconductor devices difficult or not feasible, since existing methods for RIE are often either too slow for efficient processing or result in surfaces that are substantially non-planar, pitted, and generally not conducive to nIR microscopy. For example, prior applications for RIE have been limited in substrate removal rate to about 0.4 micrometers per minute. Such removal rates are not acceptable for efficient processing. In addition, methods for back side RIE often require the time it takes the etch process to reach the endpoint be known in order to determine when to stop etching.
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment, the present invention is directed to a method for analyzing a semiconductor device having a back side and a circuit side opposite the back side. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. An ion gas comprising SF6 and N2 is directed at a target region in the back side. Using the ion gas, the target region in the back side is selectively etched using reactive ion etching (RIE) and an exposed region is formed. The etching is selective to the bulk silicon. The epitaxial silicon is used as an endpoint indicator of the step of selectively etching, and the circuitry is accessed via the exposed region.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.